1. Field of the Invention
The present invention generally relates to the general problem of designing programmable counters. More particularly, this invention relates to a circuit and a method for unique programmable counters which provide half-integral as well as integral steps.
2. Description of the Prior Art
There are plenty of counters available that divide by integers that can be programmed to change in steps of one such as by 2,3,4,5,6 and so on. Typically, programmable counters utilize a sub-component or counter such as a binary counter, a ripple counter, a modulo k counter, etc. This sub-component is surrounded by logic gates such as NANDs and exclusive-OR gates. In addition, the prior art programmable counters typically contain a digital bus or writeable/readable storage registers which provide the programmable value to be counted up to or down to. Programmable counters with integral steps are quite common in literature. However, those with half-integral steps are not described yet. Such a counter can have some very useful application that will be described later.
U.S. Pat. No. 6,226,295 (Morzano) “High Speed Programmable Counter” describes a digital counter which has a provision for starting and stopping. This allows the counter to be configurable to any integral length.
U.S. Pat. No. 6,026,140 (Owen) “Low Power Programmable Ripple Counter” describes a ripple counter which becomes programmable by use of intervening circuitry which selectively inhibits state transitions according to an initial programming step.
U.S. Pat. No. 5,809,290 (DeRoo, et al.) “Programmable Hardware Counter” describes a programmable hardware timer or counter which provides a relatively consistent measure of predetermined time intervals over a relatively wide range of performance levels.
U.S. Pat. No. 5,719,798 (Lutz, et al.) “Programmable Modulo k Counter” describes a modulo-k counter or frequency divider that produces an output pulse for every k clock pulses. The counter is programmable and synchronous, and is faster than other programmable frequency dividers.